FIG. 1 is a view showing a circuit example of a conventional solid state image pickup device 900 comprising only N-type MOS.
The solid state image pickup device 900 shown in FIG. 1 adopts a structure such that the incident light is converted into a voltage by a pixel unit 10, the voltage variation caused among pixels is reduced by a noise cancellation unit 40, and the voltage is successively outputted by a signal output unit 50.
More specifically, as shown in FIG. 1, the solid state image pickup device 900 includes: a plurality of pixel units 10 (shown is one of them) that are arranged two-dimensionally; a plurality of noise cancellation units 40 (shown is one of them) provided one for each column; and the signal output unit 50.
The pixel unit 10 includes: a photodiode PD that converts the incident light into a charge; a transfer transistor Q11 that reads out the charge from the photodiode PD; a floating diffusion FD that temporarily accumulates the charge; a reset transistor Q12 that initializes the floating diffusion FD to a power supply voltage VDD; an amplifier Q13 (referred to also as a source follower SF) that detects the accumulated charge of the floating diffusion FD as a voltage; a row selection transistor Q14 that transfers the voltage outputted from the amplifier Q13, to a row signal line Ln for each row.
A load transistor Q21 is connected to the row signal line Ln. The incident light is converted into a voltage by the pixel unit 10, and is transferred to the succeeding noise cancellation unit 40.
The noise cancellation unit 40 includes a sample hold transistor Q31, a clamp transistor Q42, a clamp capacitor C41 and a sample hold capacitor C42, and obtains the difference between the initialization voltage of the floating diffusion FD detected by the pixel unit 10 and the voltage detected by the accumulated charge transferred from the photodiode PD to the floating diffusion FD, thereby detecting a signal component from which noise components are removed; the signal component is transferred to the succeeding signal output unit 50.
The signal output unit 50 includes a column selection transistor Q51 that successively selects the horizontal signal line Ln of each column, a horizontal signal line parasitic capacitor C51, a horizontal line initialization voltage RSD, a horizontal line initialization transistor Q52 and an output amplifier AMP, successively selects the signal component, of each column, from which the noise components are removed, and outputs it to the outside through the output amplifier AMP.
Next, the operation of the solid state image pickup device 900 will be described.
FIG. 2 is a chart showing the driving timing to drive the transistors of the solid state image pickup device 900.
At a time to, a RESET pulse in the pixel unit 10 is turned on to supply the power supply voltage (VDD) to the floating diffusion FD. At this time, a signal (the node SIG1 of FIG. 1) from the source follower (SF) with the floating diffusion FD as the gate is supplied to one end (the node SIG2 of FIG. 1) of the capacitor C41 of the noise cancellation unit 40 by turning on a VSEL pulse and an NCSH pulse in the noise cancellation unit 40. At this time, by turning on an NCCL pulse at the same time, a constant clamping voltage (NCDC) is supplied to the other end (the node SIG3 of FIG. 1) of the capacitor C41, whereby the capacitor C41 is charged.
Then, at a time t2, the RESET pulse and the NCCL pulse are turned OFF.
At a time t3, the charge accumulated in the photodiode PD that converts light into an electric signal is transferred to the floating diffusion FD by turning on a TRAN pulse. By the potential of the floating diffusion FD being changed by Δ V1 from the VDD level, the signal (the node SIG1 of FIG. 1) from SF is also changed by Δ V2, and the signal where the variation among the threshold values of SFs is canceled is also supplied to one end (the node SIG2 of FIG. 1) of the capacitor C41 of the succeeding noise cancellation unit 40. Further, the signal (the node SIG3 of FIG. 1) at the other end of the capacitor C41 is also changed by a signal amount similar to Δ V2; at this time, a capacitance distribution with the capacitor C42 connected to the same node occurs, and the actual signal change amount is reduced to a signal amount Δ V3 which is the product of Δ V2 and C41/(C41+C42).
Then, at a time t4, the horizontal signal line (the node SIG4 of FIG. 1) in the signal output unit 50 is fixed at a constant voltage by turning on an RS pulse.
At a time t5, by turning on an HSEL pulse, the signal Δ V3 charged to the capacitor C42 becomes a signal reduced to a signal amount Δ V4 which is the product of Δ V3 and C42/(C42+C51), because of the capacitance distribution with the horizontal signal line parasitic capacitor C51, and is finally outputted from VOUT.
More specifically, at the time t1, the reset transistor Q12 of the pixel unit 10 is turned on by the RESET pulse to supply the power supply voltage VDD to the floating diffusion FD. At this time, the row selection transistor Q14 is turned on by the VSEL pulse to output a voltage (the node SIG1 of FIG. 1) corresponding to the charge of the floating diffusion FD from the source follower SF, and the sample hold transistor Q31 of the noise cancellation unit 40 is turned on by the NCSH pulse to supply the voltage to one end (the node SIG2 of FIG. 1) of the clamp capacitor C41 of the noise cancellation unit 40. At this time, the clamp transistor Q42 is turned on by the NCCL pulse at the same time to supply a constant clamping voltage NCDC to the other end (the node SIG3 of FIG. 1) of the clamp capacitor C41, whereby the clamp capacitor C41 is charged.
Next, at the time t2, the RESET pulse and the NCCL pulse are turned off.
At the time t3, the transfer transistor Q11 is turned on by the TRAN pulse to transfer the charge accumulated in the photodiode PD that converts light into an electric signal, to the floating diffusion FD. By the potential of the floating diffusion FD being changed by Δ V1 from the VDD level, the signal (the node SIG1 of FIG. 1) from the source follower SF is changed by Δ V2, and the signal where the variation among the threshold values of the source followers SF is canceled is also supplied to one end (the node SIG2 of FIG. 1) of the clamp capacitor C41 of the succeeding noise cancellation unit 40. Further, the signal (the node SIG3 of FIG. 1) at the other end of the clamp capacitor C41 is also changed by the signal amount similar to Δ V2; at this time, a capacitance distribution with the clamp capacitor C41 connected-to the same node occurs, and the actual signal change amount is reduced to the signal amount Δ V3 which is the product of Δ V2 and C41/(C41+C42).
Then, at the time t4, by turning on the horizontal line initialization transistor Q52 by the RS pulse, the horizontal signal line Lm (the node SIG4 of FIG. 1) in the signal output unit 50 is fixed at the constant voltage.
At the time t5, by turning on the column selection transistor Q51 by the HSEL pulse, the signal Δ V3 charged to the sample hold capacitor C42 becomes the signal reduced to the signal amount A V4 which is the product of Δ V3 and C42/(C42+C51), because of the capacitance distribution with the horizontal signal line parasitic capacitor C51, and is finally outputted from VOUT.
Patent Reference 1: Japanese Laid-Open Patent Application No. 2003-46865 (pages 1 to 8, FIG. 2)